1. Field of the Invention
This invention relates generally to defect capture and analysis during the manufacture of semiconductor wafers. More specifically, this invention relates to defect capture and analysis in which tools used to capture defects and tools used to analyze the captured defects utilize universal alignment marks to record positions of defects and to find the captured defects for analysis.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects caused during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increases the cost of the remaining usable chips.
A single semiconductor wafer can require numerous processing steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these processing steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these processing steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits. A major part of the analysis process is to determine if defects are caused by one of the process tools, and if so, which tool caused the defects.
As the wafer is placed into different tools during manufacture, each of the tools can produce different types of particles that drop onto the wafer and cause defects that have the potential to decrease the yield. In order to develop high yield semiconductor processes and to improve existing ones, it is important to identify the sources of the various particles that cause defects and then to prevent the tools from dropping these particles onto the wafer while the wafers are in the tools.
One approach used to identify the source of the particles is to analyze the particles as they lie on the wafer surface. A number of particle detectors have been developed to measure the number, location, and the size of the particles on the wafer surface. One type of particle detector is known as the laser surface particle detector (LSPD). However, the information provided by the LSPD, by itself, is sometimes not sufficient for identifying the source of the particles. In almost all cases, the particle must be further analyzed to identify what type of particle it is to assist in the determination of the source of the particle. A scanning electron microscope (SEM) equipped with an energy dispersive x-ray spectroscopy (EDS) system works well for measuring the morphology and chemical composition of particles. However, it is nearly impossible to find particles with a SEM on a relatively clean wafer surface. A technique was developed that uses a combination of the LSPD to locate particles on the wafer surface and the SEM/EDS system to analyze the particles. One of the combined systems is known as the Particle Analysis System (PAS) and this system and similar systems are used throughout the semiconductor industry. The PAS has been effective in identifying most particle contamination problems. However, as chip technology improves and device geometry shrinks, particles that can cause defects are also smaller. This requires that the analysis system be able to detect and analyze smaller particles. The major problem in the analysis of small particles with a PAS or similar system is the problem of finding the particles with the SEM after they have been identified by the LSPD. The limiting factor is the positioning accuracy of the LSPD, which may be insufficient to allow the SEM to use the minimum magnification to see the particles. The current industry standard is that a minimum of 1500.times. magnification is usually required on the SEM in order to see a 0.16 micron particle. For a typical CRT screen, this magnification translates to a field of view of 70.times.70 microns. This means that a particle's position must be known with an error less than 35 to 40 microns in order for the SEM to find the particle. As the position error increases, analysis time is wasted searching for particles. When the position error exceeds 100 microns an inordinate amount of time must be taken searching for particles.
A representative PAS system includes a Tencor 6200 LSPD and a JEOL 848 SEM equipped with a Kevex EDS. Typically, in such systems, a PC (personal computer) is used for data transfer between the LSPD and the SEM and for the manipulation of the data. The LSPD detects particles using a light scattering technique. The wafer is loaded into the LSPD chamber and the laser is raster-scanned over the wafer surface while the wafer is moved orthogonally to the scan direction. When the laser intersects a particle, light is scattered by the particle onto a detector. The magnitude of the light scattering signal provides information about the particle size. The measurement of the particle's position is more complicated. The position of the laser is known as a function of time and the scattering events produce a data file that contains the size and the x-y coordinates of each particle detected on the wafer surface. The wafer is then removed from the LSPD and loaded into a SEM. However, the coordinate system used by the x-y stage of the SEM is not the same as the coordinate system used by the LSPD. As a result, the wafer's orientation in the LSPD coordinate system differs from the wafer's orientation in the SEM's coordinate system. The PC must be able to transform the coordinate system used by the LSPD to the coordinate system used by the SEM.
To optimize the performance of PAS systems, it is necessary to improve the accuracy of particle position maps by reducing the targeting error. The targeting error is defined as the difference between particle positions predicted by the LSPD and the particle positions observed on the x-y stage. The source of nearly all the targeting error is caused by uncertainties in the LSPD particle map. A typical LSPD measures particle position with a resolution that exists as a rectangular region of 10 microns by 26 microns, however, this position is referenced to a less-accurately determined coordinate system. The coordinate system is aligned to the wafer in a specific orientation with respect to the wafer's center and notch positions. These positions are determined using a lower resolution (26 microns by 120 microns) measurement of the wafer's edge geometry. Ideally the alignment is insensitive to the wafer's orientation during scanning. From the uncertainties produced by resolution limits, it is expected that the LSPD will provide a relatively accurate particle position map, but one that is referenced to a significantly misaligned coordinate system. Therefore, a key step in the prior art in reducing the targeting error is to eliminate coordinate system misalignment. Another method in the prior art for reducing targeting error involves averaging multiple particle positions maps to reduce the influence of random uncertainties.
As the design rules of semiconductor manufacturing processes require semiconductor devices to achieve even higher densities, as more layers and interlayer dependencies are added, and as processes become increasingly complex, the role of miniscule optically unresolvable defects will move to the forefront of yield limiting problems. These defects are caught and reported by a variety of scan tools at various layers or operations in a semiconductor process flow. Since these scan tools have a specific purpose, that is, finding defects, they are generally poor at analyzing the defects caught. Another set of tools, including SEM, TEM, Auger, FIB, high-resolution optical microscopes, UV scopes are used to analyze the defects caught by the scan tools. The purpose of the two sets of tools is to quickly determine the root cause and elimination of defects.
Current practice in the semiconductor industry for finding and assigning locations to defects caught by a scan tool is non-standard and inconsistent with each individual equipment vendor developing techniques as varied as the tools are themselves. Some systems align themselves to a reticle pattern on the wafer, positioning all defects caught in relation to an absolute 0,0 die location which is arbitrarily assigned based on the original alignment position selected by the person who sets up the recipe to be the center. Other systems assign the 0.0 location such that all die are described as being in the positive x,y, quadrant. Other systems attempt to find the exact center of a wafer by performing a 3 point alignment using the edges of the wafer and using geometry to find the center. Many, if not all of these methods do not attempt to take into account the orientation of the notch (or wafer flat) when assigning their coordinate systems. Also, many of these systems are not accurate enough to place the defect within the tolerances needed for many CIM base yield models, or for recapture on a high magnification analysis tool.
The problem of trying to recapture a defect on an analysis tool that was originally caught by a scan tool still exists. Since, for the most part, defects are arbitrarily "placed" by a scan tool with a totally independent coordinate system, it is virtually impossible for an analysis tool to recapture the defects without many frustrated hours of attempts to "align" the wafer to the coordinate system used by the analysis tool. Many algorithms have been developed to translate one coordinate system to another, but these are not perfect and are considered bandages to the overall problem. This requires, however, that the vendor of an analysis tool must provide a translation algorithm for each scan tool that may be used to scan for defects.
Therefore, what is needed is universal global alignment system that would be incorporated by the vendors of each scan tool and the vendors of each analysis tool.